A High Speed Low Power 10T SRAM with high Robustness

Abstract

In this paper, a High Speed Low Power 10TSRAM (HS10T) with good read stability and write ability is proposed. The proposed SRAM (Static Random Access Memory) circuit uses single-ended bit line paths for the read and write operations. HS10T has a strong cross coupled structure of standard inverter with stacked transistor and Schmitt-Trigger (ST) based inverter, which improves the speed of operations as well as low power consumption. The transistors are sized to optimize the delay, area and power consumption of the cell configuration. The performance of the proposed SRAM is verified using a 250nm Tanner EDA (Electronic Design Automation) tool with 2.5 volts as input. Compared to the similar 10TSRAM, the proposed HS10T cell has a higher noise margin, more speed and lower
power consumption.